Toolset for nano-reconfigurable computing

Contrasting with the extensive research focusing on nano-devices properties and fabrication, not enough attention is probably given to computing architectures for these devices. This paper describes a method for mapping an FPGA architecture to a nano-device called NASIC (for Nano-ASIC). This mapping is an illustration of the interest of nano- and micro-architecture models stacked to quickly obtain CAD environments for the investigated technologies.