Article ID Journal Published Year Pages File Type
542220 Microelectronics Journal 2011 8 Pages PDF
Abstract

In this work we present a low-power, low-area and high-speed fully CMOS quadrature clock generator for on-chip SerDes applications. The device utilizes a couple of differential prescalers for high speed frequency division and four duty cycle adjusters to set the duty cycle of the produced clock signals at 50% of the clock period. The circuit was implemented with the STMicroelectronics 65 nm process technology using only 125 transistors and it occupies an active area of under 2.34 μm2. With a power supply of 1.1 V the complete circuit consumes 89.56 μW at room temperature.

► Four-phase clock generators are employed for low-noise and low-power applications. ► Four-phased clocks duty cycle has to be 50%. ► The clocks must show a 90° phase shift between them. ► Low-power, low-area, high-speed and full output swing four-phase clock generators can be constructed with differential prescalers and duty cycle adjusters.

Related Topics
Physical Sciences and Engineering Computer Science Hardware and Architecture
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