Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
542379 | Microelectronics Journal | 2006 | 5 Pages |
Abstract
An analytical model for threshold voltage (Vth) and minimum gate voltage (Vtl) of Si/SiGe MOS-gate delta-doped HEMT is presented in this letter. The model is valid for any width of the delta-doped layer and any distance of the layer from the Si/SiO2 interface. Using the model, Vth and Vtl of a Si/SiGe MOS-gate delta-doped HEMT of known dimensions are calculated. To investigate the effect of variation of the width of the delta-doped layer, the threshold voltage and the minimum gate voltage have been plotted against the width. Medici™ simulation have been performed on the same device to evaluate Vth and Vtl for different delta-doped layer widths. The simulation results are in good agreement with the results found using the analytical model.
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Hardware and Architecture
Authors
Mohmmad T. Alam, S.K. Islam,