| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 542420 | Microelectronics Journal | 2006 | 7 Pages |
Abstract
In this contribution we present a new CORDIC architecture called 'semi-flat' which reduces considerably the latency time and the amount of hardware. In our semi-flat architecture the first rotations are executed with an unfolded scheme but the remaining iterations are flattened using a fast redundant addition tree. Detailed comparisons with other major contributions show that our semi-flat redundant CORDIC is 30% faster and occupy 39% less silicon area.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
H.S. Kebbati, J.Ph. Blonde, F. Braun,