A low-power ADPLL using feedback DCO quarterly disabled in time domain

We propose a low-power ADPLL (all-digital phase-locked loop) using a controller which employs a binary frequency searching method in this paper. Glitch hazards and timing violations which occurred very often in the prior ADPLL designs are avoided by the control method and the modified DCO (digital-controlled oscillator) with multiplexers. Besides, the feedback DCO is disabled half a cycle in every two cycles so as to reduce 25% of dynamic power theoretically. The proposed design is implemented by only using the standard cells of a typical 0.18μm CMOS process. The feature of power saving is verified on silicon to be merely 1.53 mW at a 133 MHz output.