A compact low-power 4-port register file with grounded write bitlines and single-ended read operations

•A novel compact bitcell is proposed for register files that operate over moderate voltage range.•Write bitlines are driven to ground in standby to reduce bitcell leakage currents.•Clock circuits are disabled for non-accessed half of array to limit active power.•Active power is reduced by 19.6% and area of array is reduced by 17.8%.

An area-efficient 4-port register file with low power consumption is presented for mobile application processors. Area efficiency at array level is achieved with a novel compact bitcell that supports single-ended one-sided read operations using the direct read access mechanism and single-ended write operations. A write-assist technique ensures robust operation down to 0.75 V. Single-ended one-sided read operations help maintain sufficient bitcell stability at 0.75 V. Factors that contribute toward low power consumption include grounded write bitlines, bitcells with low leakage currents, individual read clock generators for top and bottom halves of the array, and smaller wordline buffers and capacitance due to a smaller bitcell. For a 2-Kib array implemented in TSMC 65 nm low power (LP) dual-Vt CMOS process, the proposed design achieves 17.8% reduction in silicon area, 19.6% lower active power, and 12.8% lower standby power when compared to the conventional 4-port dual-Vt register file. These benefits are obtained by trading off operating frequency at voltages below the nominal, read and write bitcell noise margins, and data retention voltage.