Article ID Journal Published Year Pages File Type
542564 Integration, the VLSI Journal 2016 8 Pages PDF
Abstract

•A novel method for designing RNS reverse converters for arbitrarily long moduli sets.•Two approaches to reduce the modular constant multiplication of the CRT.•ADP improvements up to 2.7 times for dynamic range of 10n-bits.•Two level approach able to efficiently scale for larger moduli sets and n.

In the last years, research on Residue Number Systems (RNS) has targeted larger dynamic ranges in order to further explore their inherent parallelism. In this paper, we start from the traditional 3-moduli set {2n,2n−1,2n+1}{2n,2n−1,2n+1}, with an equivalent 3n-bit dynamic range, and propose horizontal and vertical extensions to scale the dynamic range and enhance the parallelism according to the requirements. Two different methods to design general reverse converters for extended moduli sets to the desired dynamic ranges are introduced. Previous converters require complex weight selection of the inputs or complex final conversion steps. In this work the weight selection of the multiplicative terms associated to the inputs is reduced to additions of 2n-bit length and the final conversion step requires only one comparison. Experimental results suggest that the proposed approaches achieve significant area reductions, up to 61% lower area reductions, in comparison with the state-of-the-art for generic DR purposes. Despite having identical delay metrics as the existing generic state of the art, Area-Delay-Product efficiency metrics improvements up to 2.7 times can be achieved. The obtained results also validate the improved scalability of the proposed approaches, allowing for better results with the increase of n and the DR.

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Physical Sciences and Engineering Computer Science Hardware and Architecture
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