Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
543369 | Microelectronics Journal | 2012 | 9 Pages |
Abstract
A design methodology for monolithic integration of inductor based DC–DC converters is proposed in this paper. A power loss model of the power stage, including the drive circuits, is defined in order to optimize efficiency. Based on this model and taking as reference a 0.35 μm CMOS process, a buck converter was designed and fabricated. For a given set of operating conditions the defined power loss model allows to optimize the design parameters for the power stage, including the gate-driver tapering factor and the width of the power MOSFETs. Experimental results obtained from a buck converter at 100 MHz switching frequency are presented to validate the proposed methodology.
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Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Vitor Costa, Pedro Mendonça dos Santos, Beatriz Borges,