Assessment of structure variation in silicon nanowire FETs and impact on SRAM

Impact of device structure variability of silicon nanowire FETs is assessed and SRAM design implication is presented based on 3-D numerical simulation. Both the conventional and junctionless nanowire FETs are shown to be sensitive to structural variation whereas the former is more tolerable. Both the circular wire and non-circular wire cases for feasible SRAM design with a focus on read/write noise margin are included in our study.