CMOS design and analysis of low-voltage signaling methodology for energy efficient on-chip interconnects

This paper provides a comparative study of the low-voltage signaling methodologies in terms of delay, energy dissipation, and energy delay product (energy×delay)(energy×delay), and sensitivity technology process variations, and noise. We also present the design of two symmetric low-swing driver–receiver pairs for driving signals on the global interconnect lines. The key advantage of the proposed signaling schemes is that they require only one power supply and threshold voltage, hence significantly reducing the design complexity. The proposed signaling schemes were implemented on 1.0 V 0.13μm CMOS technology, for signal transmission along a wire-length of 10 mm. When compared with other counterpart symmetric and asymmetric low-swing signaling schemes, the proposed schemes perform better in terms of delay, energy dissipation and energy×delayenergy×delay.