Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
543660 | Microelectronics Journal | 2009 | 10 Pages |
Abstract
This paper presents a hardware implementation of a fully synthesizable, technology-independent clock generator. The design is based on an ADPLL architecture described in VHDL and characterized by a digital controlled oscillator with high frequency resolution and low jitter. Frequency control is done by using a robust regulation algorithm to allow a defined lock-in time of at most eight reference cycles. ASICs in CMOS AMS 0.35μm and UMC 0.13μm have been manufactured and tested. Measurements show competitive results to state-of-the-art mixed-signal implementations.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
H. Eisenreich, C. Mayr, S. Henker, M. Wickert, R. Schüffny,