Superjunction LDMOS on thick-SOI technology for RF applications

The feasibility of applying the superjunction (SJ) concept to a thick-SOI LDMOS transistor for RF base station applications is studied in this paper. The electrical performances of SJ thick-SOI LDMOS transistors are compared with those of the conventional RF LDMOS counterparts through an extensive 3D simulation work in terms of transconductance (gm), specific-on resistance (RON), voltage capability (VBR) and C–V characteristics. It is expected that SJ thick-SOI LDMOS structures will exhibit a significant RON reduction thanks to the N-doping concentration increment in the drift region. The charge balance in structures integrated on thick-SOI substrates with a P-type epitaxial layer requires a fit of the N and P pillar doping concentration, being the P pillar slightly lower doped than the N one. Variation of pillars doping concentrations is directly related to the device performance. Therefore, the RON/VBR trade-off and the RON components and the Cgd evolution are shown as a function of pillar doping ratio.