Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
543880 | Microelectronics Journal | 2007 | 4 Pages |
Abstract
This paper presents the design of high-voltage NMOS and PMOS devices with shallow trench isolation (STI) in standard 0.25 μm/5 V CMOS technology. Breakdown voltages of 20 V for n-channel device with a specific on resistance of 1.06 mΩ cm2 and −20 V for p-channel device with a specific on resistance of 2.83 mΩ cm2 have been achieved without any modification of existing standard CMOS process.
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Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Xiaoliang Han, Chihao Xu,