| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 544169 | Microelectronics Journal | 2006 | 9 Pages |
Environmental concerns as well as legal constraints have been pushing research on flip chip technology towards the development of lead-free solders and also to new deposition techniques [Z.S. Karim, R. Schetty, Lead-free bump interconnections for flip-chip applications, in: IEEE/CPMT 1nternational Electronics Manufacturing Technology Symposium, 2000, pp. 274–278, P. Wölflick, K. Feldmann, Lead-free low-cost flip chip process chain: layout, process, reliability, in: IEEE International Electronics Manufacturing Technology (IEMT) Symposium, 2002, pp. 27–34, M. McCormack, S. Jin, The design and properties of new, pb-free solder alloys, in: IEEE/CPMT International Electronics Manufacturing Technology Symposium, 1994, pp. 7–14, T. Laine-Ylijoki, H. Steen, A. Forsten, Development and validation of a lead-free alloy for solder paste applications. IEEE Transactions on Components, Packaging, and Manufacturing technology, 20(3) (1997) 194–198, D. Frear, J. Jang, J. Lin, C. Zhang, Pb-free solders for flip-chip interconnects, JOM, 53(6) (2001) 28–32].Binary and ternary tin alloys are promising candidates to substitute lead-content components. In this paper, we describe an electroplating technique for high density FlipChip packaging [M. Bigas, E. Cabruja, Electrodeposited Sn/Ag for flip chip connection, CDE (2003)]. An analysis using Auger Electron Spectroscopy (AES) together with additional Energy Dispersive Xray analysis (EDS) tests and Scanning Electron Microscope (SEM) analysis have been performed to optimize the reflow process of the electrodeposited bumps.
