vfTLP-VTH: A new method for quantifying the effectiveness of ESD protection for the CDM classification test

A new methodology for quantifying the effectiveness of CDM protection circuits and CDM robustness of I/O circuits is presented in this paper. This method, referred to as the vfTLP-VTH, consists of applying vfTLP stresses to test structures composed of the ESD protection and the device or circuit to be protected: a MOS device or a MOS inverter. The protected structures are used as monitors and shifts in their characteristics, such as MOS threshold voltage VTH and saturation current IDD, are used to probe device failure criteria.