Strain engineering for bumping over IPs: Numerical investigations of thermo-mechanical stress induced mobility variations for CMOS 32 nm and beyond

In this paper, numerical investigations of the mechanical effect of the bumping process on the electrical performances of transistors are performed. This aims to forecast mobility changes and to provide guidelines on the design rules for MOSFET placements within the die. Hence, starting from thermo-mechanical simulations of the process, piezoresistive theory is employed to evaluate carrier speed variations. Insights are provided for both nMOS and pMOS types, and discussion is proposed regarding their relative effect of their location with respect to the bump. Comprehensive analysis is conducted on a typical case, and complemented by a design of experiments to explore the effects of the assembly layout. Results show that the bumping process induces significant stress values, which would be responsible for introducing electrical variability of several percents. As a consequence, care must be taken while defining transistor placement and the package layout should not be ignored. Readers will find suggestions for exclusion areas for IPs placements in flip-chip product, and trends for early phase of technology development.