Investigation of the shift of hot spot in lateral diffused LDMOS under ESD conditions

This paper investigates the thermal behavior and thermal distribution of the high voltage LDMOS under Electrostatic Discharge (ESD) stress. It shows that the hot spots shift in both two-dimension and three-dimension during the snapback behavior and these spots are potential failure positions for the inferior structures. According to the different breakdown position, two improved adaptive structures which are verified by the simulations and experiment results are proposed. The article makes contribute to design more robust ESD protection power devices. The high voltage LDMOS is demonstrated in 0.5 μm CDMOS technology.