Modeling the effect of barrier thickness and low-k dielectric on circuit reliability using 3D model

The continuous scaling down of the device size and escalating circuit speed drives the requirement for EM-resistant Cu interconnect with diffusion barrier and the low-k dielectric. The study of barrier layer thickness and low-k dielectric effect in a complete 3D circuit is necessary as the actual physical implementation of an integrated circuit in a wafer is indeed 3D in nature. This paper investigates the effect of barrier layer thickness and low-k dielectric on the circuit reliability of a complete 3D circuit model. It was found that the maximum atomic flux divergence (AFD) value increases with decreasing barrier layer thickness, which implied a shorter EM lifetime with thinner barrier. Low-k dielectric will give a higher maximum AFD due to higher stress gradient, and thus a shorter EM lifetime.