| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 545231 | Microelectronics Reliability | 2010 | 6 Pages |
Abstract
We report on the reliability of InP HBT technology which has applications in very high-speed ICs. This work presents the storage accelerated aging tests results performed on InP/InGaAs HBT at stress temperatures of 180, 210 and 240 °C up to 3000 h. We have performed aging tests for two generations of InP HBT which differ from the collector doping level and from material used for planarization. From the Gummel plots, we note that the major degradation mechanism is located at the base–emitter junction periphery. Investigations on the physical origin of the observed failure mechanism has been performed using TCAD simulations.
Related Topics
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Authors
G.A. Koné, B. Grandchamp, C. Hainaut, F. Marc, C. Maneux, N. Labat, T. Zimmer, V. Nodjiadjim, J. Godin,