Processing assessment and adhesion evaluation of copper through-silicon vias (TSVs) for three-dimensional stacked-integrated circuit (3D-SIC) architectures

Through-silicon vias (TSVs) are critical components in most 3D architectures. In this paper, fully filled cylindrical Cu TSVs with a diameter of 5 μm and a depth of 25 μm were used to demonstrate quantitative assessment of the fabrication process and the interfacial adhesion of the TSVs. For TSV fabrication, the coverage of barrier and seed layers was respectively examined through dilute HF dipping and copper decoration plating. The adhesion between the TSVs and the substrate, which is of great importance for the functionality and long-term reliability of the TSVs, was characterized by four-point bending in combination with fractographic analysis. The scanning electron microscopic (SEM) images of the fracture indicate that the top of a TSV has better adhesion than the rest. This can be due to the non-uniformity of sidewall roughness and barrier thickness. A degradation of adhesion at the top was observed after thermal cycling tests, which seems to confirm the hypothesis of the influence of the roughness. These reliability tests should be taken as additional criteria for the assessment of TSV properties.