Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
545300 | Microelectronics Reliability | 2011 | 6 Pages |
This articles details investigation into metal voiding observed on electroplated gold interconnect during high temperature wafer-scale bake. The test structures and methodology to measure this effect are discussed in detail. Various factors affecting a metal voiding phenomenon were examined and measured. A drainage ratio is defined to quantify the effects of test structure layout proportions on gold void formation. Different metal formulations were also investigated to better comprehend the influence of metal composition on gold void formation. Furthermore the effect of temperature on void formation was studied and an activation energy of 2.0 eV was estimated for this phenomena. Several methods are proposed to minimize any reliability impact from this phenomenon.