| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 545412 | Microelectronics Reliability | 2010 | 8 Pages |
Abstract
Enhanced transmission speeds, lower power consumption, better performance, and smaller form factors are reported as advantages in many devices and applications when using 3D integration. One core technique for performing 3D interconnection is stacked bonding. In this paper, wafer-level bonding technologies are reviewed and described in detail, including bonding materials and bonding conditions. The corresponding 3D integration technologies and platforms developed world-wide are also organized and addressed.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Cheng-Ta Ko, Kuan-Neng Chen,