Trapped charge and stress induced leakage current (SILC) in tunnel SiO2 layers of de-processed MOS non-volatile memory devices observed at the nanoscale

In this work, Conductive Atomic Force Microscope (CAFM) experiments have been combined with device level measurements to evaluate the impact of an electrical stress applied on MOS structures with a 9.8 nm thick SiO2 layer for memory devices. Charge trapping in the generated defects and leakage current measured at the nanoscale have been correlated to the measurements obtained on fully processed MOS structures.