Soft error recovery in simplex and triplex memory systems

This paper analyzes and compares the reliability and MTTF of four fault-tolerant memory configurations subject to soft errors, namely (i) the SEC protected RAM (SEC-RAM), (ii) the SEC-unprotected triplex RAM (TMR-RAM), (iii) the triplex SEC-protected RAM (TMR-SEC RAM) and (iv) the SEC-protected triplex RAM (SEC-TMR RAM). The last two configurations are new and their difference lies on the order of performing the voting and decoding operations. Depending on the configuration, memory modeling is accomplished by Markov models either at the bit or at the word level, by also taking into account the canceling of soft errors due to subsequent soft errors. Exact theoretical expressions for the reliability and MTTF of the SEC-RAM and TMR-RAM are developed and two alternative recursive algorithms are given to assess the impact of memory scrubbing on MTTF. The advantage of both the proposed configurations is that they can tolerate all possible error patterns with three errors and they also present a remarkable resistance to error patterns with a much larger number of errors. As the analysis of the SEC-TMR RAM cannot be accomplished theoretically, due to the varying error-patterns of the SEC decoder output for more than one error in a codeword, a fast error-pattern generation algorithm (FEP) is developed. Simulation results show that there exist numerous multiple-bit error patterns in more than two words in the SEC-TMR RAM that upon decoding and voting produce the correct data-word. A comparison of the multiple-bit error masking capability of the TMR-SEC and SEC-TMR is also given.