Passive reference-sharing SAR ADC

Charge-redistribution successive approximation register (SAR) analog-to-digital converters (ADCs) are widely used for their simple architecture, inherent low-power consumption and small footprint. Several techniques aiming to reduce the power consumption, to increase the speed, and to reduce the capacitance spread have been developed, such as splitting the digital-to-analog converter (DAC) capacitor array, and charging and discharging the DAC capacitors in multiple steps. In this paper, a fully differential, low-power, passive reference voltage sharing SAR ADC architecture is presented, along with its theoretical analysis and test results. In this architecture, suitable for low sampling rate and low-resolution applications, the reference voltage is scaled down by successively connecting equally sized capacitors in parallel, allowing the use of small capacitor for its implementation. The implemented 6-bit ADC is one of the smallest ADCs reported in a 180-nm technology, and features a FoM between 30.8 and 39.3 fJ per conversion step without considering the clock generator power consumption.