Article ID Journal Published Year Pages File Type
545721 Microelectronics Journal 2014 12 Pages PDF
Abstract

A dual-mode power and performance optimized SRAM is presented. Given the fact that the power and speed associated with the cell access time are directly related to the sense amplifier offset a new optimization platform based on the hybrid offset-cancelled current sense amplifier (OCCSA) [1] is presented. It is shown that the speed and power overhead of the offset cancellation can be optimized in a multi-variable auto-calibration loop to achieve the lowest power or the highest performance mode. The flexibility of having two degrees of freedom in OCCSA offers a significant bitline delay reduction with minimum power sacrifice in the high performance mode. The proposed scheme is verified using a macro cell implemented in a 0.18 μm CMOS technology. In the Power Optimized mode, a wide range of offset is applied to a single column test structure and 25% energy consumption reduction is measured compared to the conventional case. For a 32 kb SRAM array, compared to a conventional sense amplification, a 2X reduction in energy consumption is achieved in the Energy Optimized mode. Thanks to the offset cancelling nature of the proposed scheme, a 2X improvement in cell access time is achieved in the Speed Optimized mode.

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Physical Sciences and Engineering Computer Science Hardware and Architecture
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