| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 545734 | Microelectronics Reliability | 2008 | 4 Pages |
Abstract
The effect of different diode geometries and metal patterns on the failure current It2 is investigated experimentally. The devices considered are N+/P well LOCOS diodes having different lengths, widths, finger numbers, and metal connections. The results provide useful insights into optimizing the diode for robust electrostatic discharge (ESD) protection applications.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
You Li, Juin J. Liou, Jim Vinson,