| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 545791 | Microelectronics Reliability | 2008 | 4 Pages |
Abstract
In this report, the effective gate tab size on pMOSFET to reduce HEIP degradation was investigated. As a result, the effects of tab size of STI edge have been studied and we could propose a design guide taking into account both reliability and process margin as a part of the design for reliability (DFR).
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Jung-Eun Seok, Hyun-Joo Kim, Jae-Yong Seo, Sam-jin Hwang, Byung-Heon Kwak,