Negative bias temperature instability in n-channel power VDMOSFETs

Negative gate bias is used in some applications for faster switching off the n-channel MOS devices. It is shown in this study that NBT stress-related instability in commercial n-channel power VDMOSFETs could be actually more serious than in corresponding p-channel devices. NBT stress is found to create equal VT shifts in both device types, whereas the subsequent positive bias annealing results in more serious overall VT instability in n-channel devices. The changes in the densities of stress-induced interface traps in two device types are equal as well, but significant amounts of NBT stress-induced border traps are only found in n-channel devices. All the results are discussed in terms of hydrogen reaction and diffusion model.