| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 545860 | Microelectronics Reliability | 2008 | 4 Pages |
Abstract
The thermal distribution in large DMOS output transistors of a half-bridge driver IC fabricated in smart-power SOI technology is investigated by the backside transient interferometric mapping (TIM) technique during its thermal shutdown process. The TIM measurements uncovers four hot spots, where the temperature exceeds the limit of the built in temperature sensor. This explains the specific failure mode which was identified during accelerated reliability tests. The TIM results are complemented by temperature measurements with the build-in temperature sensors.
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Authors
M. Heer, P. Grombach, A. Heid, D. Pogany,