An analytical model for hot carrier degradation in nanoscale CMOS suitable for the simulation of degradation in analog IC applications

Channel hot carrier (CHC) degradation is one of the major reliability concerns for nanoscale transistors. To simulate the impact of CHC on analog circuits, a unified analytical model able to cope with various design and process parameters is proposed. In addition, our model can handle initial degradation and varying stress conditions, allowing the designer to estimate the impact of CHC on transistor performance for arbitrary stressing patterns. The model is experimentally verified in a 65 nm CMOS technology. Expressions to simulate the impact of transistor degradation on relevant transistor parameters like output conductance and threshold voltage degradation are presented and verified.