| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 545934 | Microelectronics Journal | 2013 | 8 Pages |
We present an analytical model of TANOS program/erase transients that can be used to implement a compact SPICE-like model of these memory devices. Simulation results obtained from a physics-based TANOS model are used to derive simple analytical formulas relating the program/erase currents and the centroid of the trapped charge distribution to operating conditions and stack composition. The model allows reproducing with a good agreement the experimental program/erase transients, thus providing a valuable tool for IC designers to optimize TANOS memory circuits, especially in the framework of multi-level applications.
► Analytical model of TANOS program/erase transients. ► Suitable for SPICE-like circuit simulations. ► Analytical equations of program/erase currents and charge centroid. ► Voltage-controlled current source to reproduce TANOS program/erase operations. ► Validated with respect to several TANOS samples.
