Gate oxide breakdown in FET devices and circuits: From nanoscale physics to system-level reliability

Gate oxide breakdown has been historically considered a catastrophic failure mechanism for CMOS technology. With CMOS downscaling the mid 1990’s have seen the emergence of soft breakdown as a possible failure mode. At the same time the notion started appearing that the first breakdown event does not necessarily spell the immediate failure of the entire CMOS application. Relaxation of the CMOS circuit reliability criteria, however, requires a thorough understanding of the impact of the breakdown path on FET behavior. This cannot be consistently achieved without the microscopic perspective of the physical effects occurring in the affected device. Future CMOS applications will be able to sustain many soft breakdown events, which will be treated as additional parametric variation. Tools ranging from simulation to circuit monitoring will assure reliability at the functional level.