| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 545986 | Microelectronics Reliability | 2007 | 4 Pages |
Abstract
We report on the excellent reliability performance of high-voltage (HV) gate stacks comprised of a thin thermal oxide and a thicker HTO layer. Time-to-breakdown of the developed stacks exceeded corresponding values for thermal HV oxides of the same thickness. Peculiarities of current relaxation in course of electrical stress tests are interpreted by injected charge trapping in HTO and new trap generation. Charge trapping in optimized HTO is low and guarantees reliable device operation.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Yosef Raskin, Asaad Salameh, David Betel, Yakov Roizin,