| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 546029 | Microelectronics Reliability | 2007 | 4 Pages |
Abstract
A detailed study of the carrier trapping properties shown by the silicon/oxynitride/oxide gate layers in PowerVDMOS technologies is reported. A quantitative analysis of hole and electron trap densities versus the specific N2O based nitridation process, extracted from Fowler–Nordheim constant current stress kinetics, allows a deep understanding of the role played by those defects in the susceptibility of every nitrided layer.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Giuseppe Currò, Marco Camalleri, Denise Calì, Francesca Monforte, Fortunato Neri,