Experimental studies of board-level reliability of chip-scale packages subjected to JEDEC drop test condition

We investigate in this paper board-level drop reliability of chip-scale packages subjected to JEDEC drop test condition B, which features an impact pulse profile with a peak acceleration of 1500G and a pulse duration of 0.5 ms. Effects of Sn–Ag–Cu or Sn–Pb solder joint compositions, fluxes, and substrate pads with Ni/Au surface finish or OSP coating on the drop reliability of the board-level test vehicle are compared. Locations and modes of the failed solder joints are examined using the dye stain test. The results indicate that solder joints with a low Ag weight content and substrate pads with OSP coating both enhance the drop resistance of the board-level test vehicle.