LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier

As the density and operating speed of complementary metal oxide semiconductor (CMOS) circuits increases, dynamic power dissipation has become a critical concern in the design and development—of personal information systems and large computers. The reduction of supply voltage, node capacitance, and switching activity are common approaches used in conventional CMOS. In adiabatic switching circuits, the current flow through transistors can be significantly reduced by ensuring uniform charge transfer over the entire available time. This paper presents the simulation of this current in two-phase clocked adiabatic static CMOS logic (2PASCL) and conventional CMOS. From the SPICE simulations, at transition frequencies from 1 to 12 MHz, a 4×4-bit array 2PASCL multiplier shows a maximum reduction in power dissipation of 77% relative to that of a static CMOS. The measurement results of a 4×4-bit array 2PASCL multiplier demonstrate a 57% reduction compared to a 4×4-bit array two-phase clocked adiabatic dynamic CMOS logic (2PADCL). These results indicate that 2PASCL technology can be advantageous when applied to low-power digital devices operated at low frequencies, such as radio-frequency identification (RFID) tags, smart cards, and sensors.