Failure analyses for debug and ramp-up of modern IC’s

Quick and successful failure analysis is a key component for in-time realization and ramp-up of new products. The structure of analysis flow from verification of failure to fault identification and corrective actions is presented with the focus on modem techniques in fault localization. For the area of design debug techniques for internal probing and circuit modification by mask less redesign are described, yield learning is demonstrated on the example of SRAM fails and scan shift loss. Finally an assessment of the future of failure analysis in this field is given.