Analysis of triggering behaviour of high voltage CMOS LDMOS clamps and SCRs during ESD induced latch-up

Current flow uniformity during ESD induced latch-up event is investigated in multi-finger LDMOS clamps and SCR ESD protection devices fabricated in a 0.6 μm high voltage CMOS process. Current flow, excess free carrier and hot spot distribution are analyzed by transient interferometric mapping technique combined with a latch-up pulse system consisting of a solid state pulser and a clear pulse unit. During latch-up, the current in the LDMOS clamps flows just in a single spot and the failure position is random and independent on device type. The position of the failure site correlates with the trigger position of the device. The SCRs exhibit pulse-to-pulse instabilities in the current flow.