| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 546222 | Microelectronics Reliability | 2006 | 4 Pages |
Abstract
A new design scheme to improve the ESD performance of high voltage tolerance (HVT) I/O is presented in this paper. Without calling for the additional process steps or modification, the proposed design enhances the ESD failure immunity by having both of the stacked nMOS transistors turned on simultaneously. The ESD characteristic of new HVT IO structure has been measured using TLP and shows the improvement in It2 to 2.2A from 0.5 A and Vt1 to 6.1 V from 11.5 V, respectively.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
