Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
546264 | Microelectronics Reliability | 2006 | 6 Pages |
This paper presents a new test circuit for hot-carrier degradation analysis based on a ring oscillator. The devices and the test circuit were fabricated using Philips’ 0.35 μm CMOS technology. For single device, AC and DC hot-carrier-induced degradation are the same if the effective stress time is carefully taken into account. For circuit level degradation, the frequency of the ring oscillator, on logarithmic scale degrades at the same slope as the saturation drain current of nMOS transistor degrades, while pMOS transistor degradation is much smaller than nMOSFET degradation and can be ignored. For universal applications, the circuit degradation can be expressed by MOSFETs Idsat degradation with NSF (nMOSFET degradation speed factor) and PSF (pMOSFET degradation speed factor). Formulae for NSF and PSF calculations are derived. Simulations with Philips PSTAR circuit simulator were also performed, which well agree with the experiment results.