Via wearout detection with on-chip monitors

This project aims to detect the onset of chip failure due to via voiding through monitoring the delays of paths in a chip. The proposed method relates the probability of failure of individual vias to an increase in delay for monitors of the system using data for 65 nm technology. The delay increase, as a function of the failure distribution parameters, the path length, gate type, and process variation, has been investigated. An on-chip, ring oscillator-based wearout monitoring circuit is presented. The proposed scheme monitors the delay through a data path using a delay detection circuit (DDC).