High speed interconnect data dependent jitter analysis

This paper focuses on modeling and characterizing the data dependent jitter (DDJ) in high-speed interconnect. The analysis process is performed based on the Fourier series using the interconnect RLC model. By calculating the pattern dependent delay deviations, the DDJ is characterized. To validate the model accuracy, the analysis results have been compared against Cadence simulations. The interconnect layout optimization is also explored to minimize the DDJ.