Cell architecture for nanoelectronic design

Nanotechnology research has already proved and implemented several nanoscale devices. However, due to high defect ratios, large parameter variability and reduced noise margins, special architectures are needed to build reliable mid/large nanocircuits. Up to date several architectures have been proposed to design circuits in the nanoscale, but they do not consider the entire nanoscale environment. In this work, we propose and analyze a cell architecture based on the averaging of multiple nanodevices which is capable of alleviating the three main problems of the nanodevices at the gate level (internal noise, device parameter variation and defects). The proposed structure has a low implementation complexity which further reduces the fabrication defects. Using this cell architecture we present 2 and 3-input NAND gates showing their output response and error probabilities. Finally, we show that it is possible to improve the cell error tolerance by taking advantage of interferences among nanodevices which reduces the standard deviation by a factor larger than N.