Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
546674 | Microelectronics Journal | 2007 | 7 Pages |
Abstract
The effect of voltage-scaling on interconnect delay minimization by CMOS-repeater insertion is analyzed. Analytical models are developed to calculate the optimum number of repeaters as function of CMOS supply voltage. The analytically obtained results are in good agreement with SPICE extracted results. Analysis shows that voltage-scaling decreases power dissipation and the optimum number of repeaters required for delay minimization in long interconnects. Both resistive and inductive interconnects have been considered. At highly scaled voltages, the inductive interconnect has the advantage of lower power-delay product. It is also seen that voltage-scaling affects delay improvement due to repeater insertion.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Rajeevan Chandel, S. Sarkar, R.P. Agarwal,