Article ID Journal Published Year Pages File Type
546846 Microelectronics Journal 2016 10 Pages PDF
Abstract

This paper presents a disturb-free 10T subthreshold SRAM cell with fully-symmetrical structure and tri-state pre-charge free bit-line (BL). The disturb-free feature facilitates bit-interleaving architecture that can reduce multiple-bit errors in a single word and enhance soft error immunity by employing error checking and correction (ECC) techniques. The fully-symmetrical cell structure provides balanced margin and performance in advanced strained-silicon and/or FinFET technologies where PMOS strength approaches that of NMOS. The tri-state BL is left floating in standby state to minimize switching activity for energy efficiency. The scheme eliminates the need of BL keeper, provides balanced two-transistor stack read for better read performance, and eases the design and migration. The proposed 10T SRAM cell is demonstrated by 128 kb SRAM macro implemented in 40 nm low-power (40LP) CMOS technology. Measured read and write functionality is demonstrated with VDD down to 0.35 V (~100 mV lower than the threshold voltage). Data is held down to 0.325 V with 2.53 µW standby power. The measured maximum operation frequency is 375 kHz with total power consumption 5.43 µW at 0.35 V.

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