An area-efficient LDMOS-SCR ESD protection device for the I/O of power IC application

•A new ESD protection device FP-LDMOS-SCR is designed with a floating P+ region.•Bath 4002 TLP test system is used to measure the I–V curve of device.•TCAD simulation is applied to analyze the operation mechanism.•The It2 of the new device is improved a lot compared to normal LDMOS-SCR device.

Lateral Double diffused Metal Oxide Semiconductor (LDMOS) transistors are widely used in HV output circuit and its Electrostatic Discharge (ESD) problem have been well studied. LDMOS embed Silicon Controlled Rectifier (LDMOS-SCR) can be used to improve LDMOS ESD robustness. In order to further enhance the ESD self-protection capability of LDMOS-SCR, a new device LDMOS-SCR with a floating P+ implant region (FP-LDMOS-SCR) is proposed in this paper. Due to the floating P+ implant region is placed near the drain end, It2 of the new FP-LDMOS-SCR device increases obviously, compared with traditional LDMOS and LDMOS-SCR devices. The FP-LDMOS-SCR′s It2 with one floating P+ is 1.3 A and that with two floating P+ is 2.7 A. The results of Technology Computer Aided Design (TCAD) simulations will be presented in this paper to help analysis the physical mechanism and observe the ESD behavior of the LDMOS-SCR. The proposed FP-LDMOS-SCR, same driver capability with LDMOS, can be applied in HV output circuit and also provide its ESD self-protection through shunted ESD stress to ground.