Investigation of ESD protection strategy in high voltage Bipolar–CMOS–DMOS process

This paper presents device optimization and physical analysis based on gate-grounded NMOS (GGNMOS) and n-channel lateral DMOS (nLDMOS) devices manufactured in a 0.35 μm 5 V/30 V high-voltage BCD process. The multiple body pick-up technique has been investigated in detail for the GGNMOS, and the robustness and effectiveness of the LDMOS device is optimized by tuning the drain contact to gate space (DCGS) and increasing the body resistance. Finally, the trigger voltage walk-in effect is observed for the nLDMOS device and is studied by comprehensive simulation and TLP tests.