Comparative analysis of yield optimized pulsed flip-flops

In this paper, the influence of random process variations on pulsed flip-flops is analyzed. Monte Carlo simulation results demonstrate that using transistor reordering and dual threshold voltage transistors timing, energy and energy-delay-product yields of more than 1.98, 1.62 and 1.99 times higher are obtained, without requiring architectural modifications and without increasing silicon area requirement. Several flip-flops optimized as described here are compared taking into account the effects due to random process variations and to environmental variations (caused by power supply voltage and temperature fluctuations). Obtained results show that among the compared circuits the Conditional Precharge Flip-Flop achieves the highest delay, energy and energy-delay-product yields.