Variability aware low leakage reliable SRAM cell design technique

This paper presents a technique for designing a low power SRAM cell. The cell achieves low power dissipation due to its series connected drivers driven by bitlines and read buffers which offer stack effect. The paper investigates the impact of process, voltage, and temperature (PVT) variations on standby leakage and finds appreciable improvement in power dissipation. It also estimates read/write delay, read stability, write-ability, and compares the results with that of standard 6T SRAM cell. The comparative study based on Monte Carlo simulation exhibits appreciable improvement in leakage power dissipation and other design metrics at the expense of 84% area overhead.

► Variability aware low power SRAM cell design technique in 22 nm technology node is presented. ► Significant improvements in read stability, write-ability and power dissipation are achieved. ► Impact of process, voltage, and temperature variations on standby power is investigated. ► Significant improvement in variability is achieved signifying reliability of proposed design.